1. Field of the Invention
The present invention relates to devices providing different types of reset, interrupt and warning signals to signal processing systems in response to power supply output levels and to initialization signals.
2. Description of Related Art
Signal processing systems, such as computers, industrial controllers and peripheral devices, are typically sensitive to output levels of power supplies driving the systems. In fact, such systems are often characterized by unique requirements for initialization control sequences, power-up and power-down control sequences, and reset sequences during power glitches. There are no standard formats for these control sequences. Therefore, designers spend a great deal of time creating circuits for generating reset, interrupt and warning signals and sequences of signals to meet the needs of the particular signal processing system being designed.
For instance, microcontrollers and microprocessors must be reset on power-up, and a reset signal must be held asserted for some time after the clock is running and logic is fully functional. Thus, for the Intel 8051 microcontroller, the reset signal must be asserted active high for 24 cycles during power-up. For the Intel 80286 microprocessor, the reset signal must be asserted active high for 16 cycles. For the Advanced Micro Devices Am29000 microprocessor, the reset signal must be asserted active low for 4 cycles. For the Motorola 68000 microprocessor, the reset signal must be asserted active low together with a halt signal active low for 10 cycles and 100 milliseconds after power-up. In the prior art, circuits implemented to ensure that reset signals are asserted for the required duration, are based on circuits built of resistors and capacitors, and some of them are also coupled with preset voltage reference comparators (see, Patterson, "Battery-Backup Circuit Offers System Reset," EDN, May 26, 1988, pp. 212-214; Barnett, "Comparator Circuit Monitors Window Events," EDN, Feb. 18, 1988, p. 235; Andraycak, "Soft-Start and Delay Protects Power Supply," EDN, Feb. 4, 1988, p. 189; and Pritchard, "Power-Fail Circuit Gives Prompt Response," EDN, Mar. 31, 1988, p. 197). Delay circuits can also be implemented using digital monostable multi-vibrators for generating output pulses of programmed output duration in response to a supplied reset signal (see McCarthy, "Digital One-Shot Has Power-On Preset," EDN, Jan. 21, 1988, p. 208).
It can be seen that these circuits are design-intensive. This is particularly true when one recognizes that signal processing systems can be exceedingly complex, requiring initialization sequences for large numbers of devices having a variety of parameters in the same system. For instance, some resets within a single system may be required to be active low, while others must be active high, some synchronized on a falling edge of the clock while others are synchronized on a rising edge. Others may require warning signals to be asserted on certain abnormal conditions of the power supply.
Accordingly, a need exists for a device simplifying the design of initialization and power supply level detection circuitry for use with signal processing systems.